One type of tester for testing integrated circuits (ICs) is an automated test pattern generator (ATPG). A typical ATPG tester generates digital waveform test patterns that are output from input/output (I/O) pins of the tester and input to I/O pins of the IC being tested. A typical ATPG has several application specific integrated circuits (ASICs), each of which contains several delay line (DL) circuits that are used to generate the digital waveforms used to test ICs. Each DL circuit includes a number of delay elements, any subset of which can be switched on to provide a given delay.
A digital waveform is typically created by logically combining the outputs of multiple DL circuits in a formatter (e.g., an Exclusive-OR (XOR) gate) to generate various types of waveforms having various duty cycles. The waveform can be altered by varying the delay settings of one or more of the DL circuits. The output of the formatter is connected to an I/O pin of the ASIC. The signal received at the I/O pin of the ASIC can be steered to an I/O pin of the tester in order to output a test signal from the tester that can be used to test logic inside of an IC.
The signal received at the I/O pin of the ASIC can also be steered to an I/O pin of the tester that is used to calibrate DL circuits contained in the ASIC. Before the ASICs that contain the DL circuits are incorporated into a tester, each DL circuit in each ASIC is calibrated at different delay settings to ensure that the DL circuit is operating properly. The I/O pin of the tester that receives the signal from the ASIC to be calibrated is typically connected to the input of an integrator circuit, which integrates the signal over many duty cycles to produce a high-precision voltage signal that is proportional to the duty cycle of the signal output from the formatter. The high-precision voltage signal is measured by a high-precision voltmeter. The duty cycle is then determined based on the value of the voltage signal.
To calibrate a DL circuit, the output of one DL circuit and the output of another DL circuit are combined by a formatter, and the output of the formatter is steered to one of the aforementioned calibration I/O pins of the tester. The output of one of the DL circuits provides the falling edge of the signal output from the formatter, and the output of the other DL circuit provides the rising edge of the signal output from the formatter. The DL circuit that is not being calibrated has its delay set to a constant delay while the DL circuit that is being calibrated will have its delay setting varied to produce signals having various duty cycles. Thus, the duty cycle of the waveform output from the formatter will vary as the delay setting of the DL circuit being calibrated is varied.
One of the problems associated with the current calibration technique and system is that calibration takes a relatively long time to be performed. A tester may have, for example, 1,000 I/O pins, each of which has an ASIC associated with it. Each ASIC may have, for example, 16 DL circuits. Therefore, a total of 1,000×16=16,000 DL circuits will need to be calibrated. In addition, for each DL circuit, typically many different delay settings will need to be calibrated. With the current calibration technique and system, typically only one of the aforementioned high-precision voltmeters is allocated to each board of the tester. Each board may have, for example, 16 ASICs and one high-precision voltmeter mounted on it. At any given time, the high-precision voltmeter can only measure the voltage signal associated with one of the ASICs on the board. Therefore, multiple DL circuits on the same board cannot be calibrated simultaneously, i.e., in parallel. Consequently, the calibration process is typically very time consuming and may take hours to perform.
Another known system for calibrating a DL circuit involves connecting the delay elements of the DL circuit to form a ring oscillator. The ring oscillator is formed by feeding the output of the last delay element in the delay line back to the input of the first delay element in the delay line. The oscillations in the waveform output from the DL circuit are counted for a fixed period of time. When the delay setting is varied, the number of oscillations that occur during the fixed period of time will vary accordingly. Thus, the change in the amount of delay produced by the DL circuit can be ascertained by counting the difference in the number of oscillations that occur during the fixed period of time when changing from one delay setting to another.
Although the ring oscillator approach enables DL calibration to be performed relatively quickly, the calibration may not be accurate due to the fact that the period of oscillation depends on the average of the rising-edge delay and the falling-edge delay. Because of device mismatching, processing condition variations and other factors, for a given setting, a DL circuit may produce one delay for rising edges and a different delay for falling edges. This creates inaccuracy in the calibration process, which makes it generally unsuitable for its intended purpose.
A need exists for a way to calibrate DL circuits that enables calibration to be performed quickly and with great precision.